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tiens, je connais pas ce forum, c'est quoi l'ambiance ? Gamoo ou NA ? 'fin si tu vois ce que je veux dire ....
I first thought that the VPU had dedicated buses for each of the SLAs, but by inspecting the pixel clock, I noticed that the bursts were happening at 100Hz instead of 50. This meant that the pixel data bus was instead shared between both displays and a select signal was used to indicate which burst was for which one (further called CS for "Chip Select").The brightness signals CLKA/B/C are also shared, along with the pixel clock and clear signals.